Avel-COVID19-Comp Sc-Hnd1- Computer Architecture
COVID – 19 SIT@HOME
INTEL. DEV. CLASS
HND COMPUTER SCIENCE
Committee of Intellectuals [CoI]
INTELLECTUAL DEVELOPMENT CONFERENCE CENTER [INTEL CENTER]
QUESTION: Addressing part of the instruction set can be implemented either by Direct or Indirect using these concept-list, Explain and support your argument in appropriate instruction, any Eight (8) indirect addressing.
- Immediate Mode
- Register Mode
- Register indirect mode
- Auto increment or Auto decrement mode
- Direct Address mode
- Indirect Address mode
- Relative Address mode
- Indexed Addressing mode
- Base register Addressing mode
- Immediate Mode
In this mode, the Operand is specified in the instruction itself. In other words, an immediate-mode instruction as an operand field rather than an address field. The operand field contains the actual operand to be used on conjunction with the operation specified the instruction.
- Register Mode
In this mode the operands are in register that reside within CPU. The particular register is selected from a register field in the instruction.
- Register Indirect Mode
In this mode the Instruction specifies register in CPU whose contents give the address of the Operand in memory. Before using a register indirect mode instruction, the programmer must ensure that the memory. Address of the operand is place in the processor register with a previous instruction.
- Auto Increment or Auto decrement mode
This is mode except that the register is incremented or decremented after for before its value is used to access memory when the address store in the register refers to a table of data is memory it is necessary to increment or decrement the register after every access to the table.
- Direct Address Mode
In this mode the effective address is equal to the address part of the instruction.
- Indirect Address Mode
In this mode the address field of the instruction gives the address where the effective address is stored in memory control fetches the instruction from memory and uses its address part to access memory again to read the effective address. Effective address = address parts of instruct + content of CPU register.
v. Relative Address mode
In this mode the content of the program counter is address to the address part of the instruction in order to obtain the effective address. When this number is added to the content of the program counter the result procures an effective address whose position in memory is relation to the address of the next instruction.
vi Indexed Addressing mode
In this mode the content of an index register is added to the address paid to the instruction to obtain the effective address.
- Base Register Addressing mode
In this mode the content of a base register is added to the address part of the instruction to obtain the effective address.
QUESTION: Briefly described the term Bus System?
A bus in computer language is way or passage over which information moves between devices. Most buses are bidirectional and devices can send or receive information. . It ordinarily approaches focuses and it typically has access points, or places into which a device can tap to become part of the channel. It allows to add new devices easily and facilitates portability of peripheral devices between different computer systems. It is a share communication link between the diverse devices.
QUESTION: Briefly describe the following types of addressing modes with examples:
(a) Direct Addressing (b) Indirect Addressing
(c)Immediate Addressing (d) Relative Addressing
(e) Register Addressing
- Direct Addressing: This deals with getting data in memory. For instance MOV, AX  loads the register AX with the 16 bit value stored in memory beginning at location 1000 hexadecimal
- Indirect Addressing: This mode accesses the memory location whose address appears in the register, rather than using the value in the source register. For example, MOV, AX, [BX] will use the value in BX as the address of the memory location where the genuine and actual operand will be found
- Immediate Addressing: This mode utilizes a prompt and immediate operand that has a constant value or an expression. For example, MOV AX, 45H, the immediate constant 45H will be transferred into Register AX OR * *
- Relative Addressing: Sometimes alluded to as PC-relative addressing mode. In this mode, thecertainly and implicitly referenced register is the program counter (PC) i.e. the next instruction address is added to the address field to produce the (EA) Effective Address. For example:
MOV x (PC), R1, the contents at address X +PC are moved to RI. V contains a constant value.
** Immediate Addressing Mode: The operand is specified in the instruction itself E.g. MOV #200, RO, places the value 200 in the Register RO
- Register Addressing: Specifies an operand on or a test of the register, without referring the memory. The operand is the contents of a register, here the operands are specified by specifying the name of the register in the instruction. For example, MOV RO, R1, contents of RO register are moved to R1 register OR
MOV Ax, Bx, Bx is the source and Ax is the destination
QUESTION: Clearly describe Von-Neumann CPU Architecture Design and state specifically its different distinct features.
Von Neumann Architecture is adesign for electronic computerized PC or digital computer or any stored programme computer in which an instruction fetch and a data operation cannot occur at the same time because they share a common bus. A stored programme computer is one that keep its programme instructions as well as it data in read write random access memory (RAM)
The parts comprising of three main components-
Central Processing Unit (CPU),
input / output (I/O) interfaces
The CPU controls the request in which directions ought to be executed and controls the retrieval of the proper operand. It interprets the instructions of the machine. The execution of each introduction is determined by a sequence of control signals produced by the control unit.
The CPU which can be viewed as the core of PC framework, incorporate three principle parts.. The control unit (CU) one or more arithmetic and logic units (ALUs) and various registers.
The ALU executes all mathematical and Boolean operations. The registers are temporary storage locations to quickly store and transfer the data and instructions being used. Because the registers are often on the same chip and directly connected to the CU. The registers have operands and as the destination of results will improve the performance.
A CPU that is implemented on a single chip is called a microprocessor
The I/O interfaces enable the PC to convey to the client and to the auxiliaryor secondary storage devices like disk and tape drives. Also allow the computer’s memory to receive information and send data to output devices. These three component are connected to each other through a collection of signal lines know as a bus. The main buses carrying information are the control bus, data bus, and address bus.
Each bus contains several wires that allows for the parallel transmission of information between various hardware components. The data bus, which is bidirectional, sends data to or from a component. The control bus consists of signals that permit the CPU to communicate with the memory and I/O devices. The address bus identifies either a memory location or an I/O device.
The PC’s memory is utilized to store a program instructions and data. Two of the commonly used type of memories are Random Access Memory (RAM) and Read Only Memory (ROM). RAM store the data and general purpose programs that the machine executes. RAM is temporary, that is, it’s contents can be changed at any time and it is erased when power to the computer is turned off. ROM is permanent and used to store the initial boot up instructions of the machine.
QUESTION: Compare the instruction set architecture in RISC and CISC processors in terms of instructions format, addressing nodes and CPI.
- CISC and RISC in tabular form below
|1. Instruction format 2. Addressing modes 3. CPI||16-64 bits per Instruction 12-24 2-15, on the average 5||fixed (32-bit) format. Limited to 3-5 <1.5, very close to 1.|
QUESTION: Define the following terms;
(a) Processor design space. (b) Latency. (c) Instruction issue rate. (d)Simple latency. (e) Resource conflicts. (f) Processor versus coprocessor. (g) GPRs.(h) Addressing modes. (i) Unified versus split caches. (j) Hardwired versus micro coded control.
- Processor design space: It is characterized as a planned space with the x and y axis. X-axis represents clock-rate and y-axis represents CPI. Each coordinate i.e., point in the space, (x, y) represents a design choice of a processor whose performance is determined by the values of the coordinates.
- Latency: It is characterized as the time required between issuing two consecutive instructions.
- Instruction issue rate: It is characterized as the number of instructions issued per cycle.
- Simple Latency: The quantity of cycles required for the execution of a simple instruction such as add, move etc is known as simple latency.
- Resource conflicts; When at least two instructions attempt to use the same functional unit at the same time then it is known as resource conflict.
- Processor versus coprocessor: A coprocessor is onethat is typically appended or attached to a processor. Coprocessor performs special functions at a fast speed. For example: Math coprocessor, graphical coprocessors etc.
- General Purpose Registers (GPRs): Those registers that are for general use of the programmer and are not designated for special usage like the special-purpose registers-base registers or index registers.
- Addressing modes: It specifies how the effective address of an operand is generated so that its actual value can be fetched from the-correct memory locations.
- Unified versus split caches: In a unified cache, both data and instructions are kept in the same cache. In a split caches, both data and instructions are held in the separate caches.
- Hardwired versus micro coded control: In hardwired control, the
signals for each instruction are generated by proper circuitry such as delay elements.
In micro coded control, each instruction is implemented by a set of microinstructions, which are stored in the control memory. The decoding of microinstructions generates appropriate signals to control the execution of an instruction.
QUESTION:Define the following terms:
(a) Instruction pipeline cycle. (b) Issue latency. (c) Issue rate. (d) Simple operation latency.(e) Resource conflicts.
(a) Instruction pipeline cycle:The clock period of the instruction pipeline.
(b) Issue latency: The time required, in cycles, between the issuing of two adjacent instructions.
(c) Issue rate: The number of instructions issued per cycle,
(d) Simple operation latency: Simple instruction like adds, loads, stores, branches, moves etc have lesser delays in execution than the complex instructions like divides, cache misses etc. These latencies are measured in number of cycles.
(e) Resource conflicts: A situation where two or more instructions demand use of the same functional unit at the same time.
QUESTION: Explain the relationship between the integer unit and the floating point unit in must RISC processors with scalar or super scalar organization?
In most RISC processors, the integer unit executes load, store, integer, bit and control transfer functions. It also fetches instructions for the floating-point unit in some systems. The floating-point unit performs various arithmetic operations on floating-point numbers. The two units can operate concurrently. Based on your understanding of advanced processor, answer the following questions on RISC, CISC, super scalar and VLIW architecture.
QUESTION: Explain briefly, the basic operations of the different categories of instruction sets
- Arithmetic Instructions, these instructions perform the tasks like: Addition and Subtract, Increment and Decrement. With this instruction set any 8-bit number, or the contents of register, or the contents of memory location can be added, subtract, increment, or decrement to the contents of accumulator. Examples: ADD B, SUB B, etc.
- Data transfer instruction, this copies the contents of the source register into the destination register, without altered the content of the source register. Example are MOV B, C or MOV B, M.
- Control instructions, these instructions control the operation of microprocessor. These instructions after the normal sequential flow sequence is transferred to the memory location specified by the 16-bit address given in the operand
- Logical instructions, these instructions perform logical operations on data stored in registers, memory and status flags. The logical operations are: AND Or, XOR, Rotate, Compare, and Complement. Any 8-bit data, or the contents of register, or memory location can logically have AND operation or OR operation and so on, and the result is stored in accumulator
QUESTION: Explain each of the following terms in your own words:
(i) Translator (ii) Interpreter (iii) Virtual machine
(i) Transistor: Translates from low level language to high level language. In computer programming, it serves as machine language and which acts as a compiler in programming converts High level language to low level language and vice-versa. Convert instructions to machine language e.g. FORTRAN programming translates signals from one point of fetch-decode-cycle to the other.
(ii) Interpreter: Used in computer fetches instruction, examine and execute instructions. Programming e.g. BASIC programming to convert instruction code to machine understandable language. Interprets signals or execution to the compiler in microarchitecture level to the bus, shifter and arithmetic logical unit in the fetch-cycle to the program counter (PC) which fetch, examines operands and then to registers in one level to another.
(iii) Virtual Machine: It is a device which store instructions temporarily before handling over to main storage system. Act as a real machine but not actually real in a computer system
QUESTION: Explain the concept of Pipelining?
Pipelining is a processor organization which the processor consists of a number of stages, allowing multiple instructions to be executed concurrently
It is a technique that allows for simultaneous execution of parts, or stages, or instructions to move efficiently process instructions
It is a technique employed in processor where the microprocessor begins executing a second instructions before the first has been completed i.e. several instructions are in the pipeline simultaneously, each at a different processing time
QUESTION: Explain a typical structure of a simple control unit of microprocessor, and it basic operations.
The control unit facilitates, coordinates, oversees and manages CPU activities, in particular the execution of instructions by the arithmetic and logic unit (ALU). It does this by issuing control signals to the other areas of the processor, instructing them on what should be performed next.
The control unit is arguably the most convoluted or complicated part of the CPU, it is in charge of controlling a significant part of the activity of whatever remains of the processor and is responsible for controlling much of the operation of the rest of the processor. To the arithmetic and logic unit, control unit can be broken down further for easier understanding. As the three main elements of the control unit are as follows:
This decode the instructions that makeup a program when they are being processed, and to determine in what actions must be taken in order to process them. These decisions are typically taken by observing at the Opcode of the instruction, together with the addressing mode used. This is shrouded in more prominent detail in the instruction execution section of this tutorial.
Timer or Clock
The timer or clock guarantees that all processes and instructions are carried out and completed at the right time. Pulses are sent to the other areas of the CPU at regular intervals (related to the processor clock speed), and actions only occur when a pulse is detected. This ensures that the actions themselves also occur at these same regular intervals, meaning that the operations of the CPU are synchronized.
Control Logic Circuits
The control logic circuit facilitates s are used to create the control signals themselves, which are then sent around the processor. These signals inform the arithmetic and logic unit and the register array what they actions and steps they should be performing, what data they should be using to perform said actions, and what should be done with the results.
QUESTION: Give advantages & disadvantages of using common/separate caches.
Advantages of Separate caches:
duplicates, the transmission capacity since two reciprocal solicitations are
overhauled in the meantime.
- It doubles, the bandwidth because two complementary requests are serviced at the same time.
- It simplifies the logic design as the arbitrations between instruction and data accesses to cache is simplified or eliminated.
3. The access time is reduced because both data and instructions can be placed close to the functional units which will access them.
For example: Instruction cache can be placed close to the instruction fetch and decode units.
Disadvantages of separate caches :
1. It muddles the issue of consistency since information and direction may exist together in a similar store square. This is valid if self-altering code is permitted or when information and guidelines are intermixed and put away in a similar store piece. To maintain a strategic distance from this we require a compiler support to guarantee that guideline and information are put away in various store pieces.
2. It complicates the problem of consistency because data and instruction may coexist in the same cache block. This is true if self-modifying code is allowed or when data and instructions are intermixed and stored in the same cache block. To avoid this we require a compiler support to ensure that instruction and data are stored in different cache blocks.
3. It may lead to inefficient use of cache memory because the -working set size of a program varies with time and the fraction devoted to data and instruction also varies. Therefore, the sum of data cache size and instruction cache size isusually larger than the size of a unified cache. So, the utilization of the instruction cache and/or data cache is likely to be lower.
Note : For separate caches three things are a must:
1. Committed data paths are required for both the data and instruction caches.
2. Isolate MMUs
and TLBs are also needed to shorten the time of address
3. A higher memory
bandwidth should be used for separate caches to support the
In practice, there is a trade off between the degree of support provided and the resulting hardware complexity.
QUESTION: How does pipelining affects system optimization
Without a pipeline, a processor gets the principal instruction from memory, performs the operations it calls for, and then goes to get the next instruction from memory and so forth. While fetching the instruction, the ALU is idle. It must wait until all instruction set have been fetched, with pipeline, the architecture allows the next instruction to be fetched while the processor is performing operations on the operands, holding the intermediate results in the buffer close to the processor until each instruction operations have been completed.
The stage of instruction fetch is continuous. The result is an increase in the number instructions that can be performed during a given time period.
Pipelining has optimized the speed of the processor in that it has improved on the rate at which processes or jobs are completed. Thus, a small penalty in instruction latency is accepted to achieve large gain in instruction throughput.
QUESTION: In one sentence each, state the major distinction between micro programmed control unit and hardware control unit.
Micro programmed control unit
micro programmed control seems to be advantageous to CISC machines, since CISC requires systematic development of sophisticated control signals, there is no intrinsic difference between these two (2) control mechanisms. Micro programmed control is a control mechanism to generate control signals by using a memory called control storage (CS), which contains the control signals.
Hard-wired control unit
The pair of “microinstruction” and “control storage address register” can be regarded as a “state register” for the hardwired control. Hardwired control is a control mechanism to generate control signals by using appropriate finite state machine (FSM). Note that the control storage can be regarded as a kind of combinational logic circuit. We can assign any 0, 1 values to each output corresponding to each address, which can be regarded as the input for a combinational logic circuit.
QUESTION: List various operating system you know and their application
- Single program: This permits just a single user program to be in main memory and processed at a time. It is available in most micro-computer based systems.
- Batch program: This gives multiprogramming to batch programs entered from terminals. The programs are executed in the sequence entered one at time.
- Multiprogramming: This term is utilized to describe the technique of having more than one program in main memory at any time and apparently being processed at the same time.
- Time sharing systems: These framework, also called multi-access systems, are on line and allow a number of users to accesses and use the computer at the same time Examples are: PC-MOS and Unix.
QUESTION: List and describe the four (4) major components of a general purpose computer
Four (4) major components of a general purpose computer
- Input & Output Devices
- Central Processing Unit (CPU)
- Main Memory (RAM/ROM)
- Backing Storage
CPU – Is the brain of the computer, where most calculations takes place (ALU). This processor determines how fast it processes tasks
Main Memory – This determines how much memory your computer can process once
Input & Output Device –
QUESTION: List and Discuss the three Identify Bus Architecture
- Data bus
- Address bus
- Control bus
Data Bus: A Bus which conveys a word or data to or from memory is known as data bus, Data lines are bi-directional. One part of the data bus runs between RAM and Micro-processor, another part of the data a bus runs between RAM and various storage devices.
Address Bus: The address conveys memory it is unidirectional, the bits flow in one direction.
Control Bus: The control bus conveys control signals between the units of the computers. The signals like RED/WRITE, START/HALT etc. are carries by Control bus.
QUESTION: Simply explain the “Fetch-Execute Cycle”.
Fetch-Execute Cycle has the following steps:
- Fetch the next instructor from the address
- Program counter
- Decode the instruction
- Execute the instruction
- Fetch the next instructor – The control unit goes to the address named in the program counter, makes a duplicate of the contents of that address, puts the copy into the instruction register, and increments the program counter.
- Decode an instruction – The control unit figures out what the instruction is and accesses any memory locations that contains operands for the instruction.
- Execute an instruction – Signals are sent to the arithmetic / logic unit to carry out the processing
QUESTION: Specifically discuss the various level of cache as it affect processor optimization.
All modern (fast) CPU (with few specialized Exceptions) have multiple levels of CPU Cache. The first CPU that used a cache had only one level of cache not split L1 Cache. They also have L2 caches and for larger processor L3 caches as well.
The L2 cache is usually not split and acts as a common repository for the already split L1 cache.
Every core of a multi-core processor has a dedicated L2 cache and is usually not shared between the cores. The L3 cache, and higher-level caches are shared between the cores and are not split. An L4 cache is currently uncommon, and is then on a separate disk even off – chip and generally on non – static random access memory (SRAM). That was also the case historically with L1 while bigger chips haves allowed integration of it and generally all cache level, with the possible exception of the last level. Each extra level of cache tends to be bigger and be optimized differently.
QUESTION: State five major functions of control unit
Function of control unit (CU) are as follow;
- Guides data flow through different computer areas
- Handles multiple tasks, such as fetching, decoding execution handling and storing results.
- Control sequential instruction execution
- Regulates and controls processor timing
- Interprets instructions
- Sends and receives control signals from other computer devices
QUESTION: What are the major three phases involve Instruction Cycle
An instruction cycle consists of the activities required to fetch and execute an instruction. The major three phases involved are: instruction fetch, instruction decode, and instruction execute.
Instruction fetch, once the program is in memory, the operating system then schedules the CPU to begin executing the program instructions. Each instruction to be executed must first be retrieved from memory. This retrieval is referred to as an “Instruction fetch”
After an instruction is fetched, it is input into a special register in the CPU, called the instruction register (IR) while (IR), the instruction is decoded to determine what type of operation should be performed. This process is referred to as instruction decode.
Instruction execution, once the instruction has been decoded, if the instruction requires operands, these are fetched from memory or possibly for other registers and placed in to the proper location (certain registers or specially designated storage areas known as buffers). The instruction is then performed, and the result are stored back into memory and /or registers. This process is repeated for instruction of the program until the program’s end is reached.
The fetch and decode activities constitute the first machine cycle of the instruction cycle. The second machine cycle begins when the instruction’s operand is read from RAM and Sends when the instruction is executed and the result written back to memory.
QUESTION: What is instruction set?
This can be described as the basic set of commands or instructions, that a microprocessor, to tell it what it needs to do. It can also be defined as a group of commands for a CPU in a machine language. This is also called command set
QUESTION: What is interrupt?
An interrupt alerts the processor to a high-priority condition requiring the interruption of the current code the processor is executing. An interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention.
QUESTION: What do you understand by? (i) MIPS (ii) Cache
(i) MIPS – Millions Instructions Per Second is an older, obsolete measure of a computer’s processor speed and power. It is a measure of instruction execution speed in terms of task performance speed compared to a reference.
- CACHE – Is a relatively small, fast-memory interposed between a larger, slower memory and the logic that access the larger memory. It holds recently accessed data, and is designed to speed up subsequent access to same data.
CACHE – Is a high speed, intelligent memory buffer that temporarily holds/stores data that the processor needs, allowing the processor to retrieve that data faster than it can from main memory. Cache consist of static RAM
QUESTION: What is your parallel computing?
In the simplest sense, parallel computing is the simultaneous use of multiple compute resources to solve a computational problem.
- To be run using multiple CPUs
- A problem is broken into discrete parts that can be solved concurrently
- Each part is further broken down to a series of instructions
- Instructions from each part execute simultaneously on different CPUs
A parallel computer is a set of processors that are able to work cooperatively to solve a computational problem. This definition is broad enough to include parallel supercomputers that have hundreds or thousands of processor, networks of workstations, multiple-processor workstation, and embedded systems. Parallel computers are interesting because they offer the potential to concentrate are computational resources, whether processors, memory, or I/O bandwidth … on important computational problems.